Synario ABEL

• Features industry leading PLD design system, ABEL, integrated within SynarioÆs Project Navigator environment, adding flexibility for device implementation, and easy reuse of existing designs for larger architectures
• ABEL Hardware Description Language (ABEL-HDL) offers design entry flexibility including state machine, logic equation, and truth table design description
• Equation simulation can be performed immediately after design entry, independent of the target device, allowing design verification before choosing a device
• Functional simulation waveforms are in easy-to-interpret display, improving design analysis methods
• Proven logic synthesis allows flexible, device independent and device dependent behavioral design, ensuring optimum design efficiency
• Automatic logic optimization supports multiple strategies of logic reduction, to efficiently utilize the most complex features of PLDs
• JEDEC simulation allows device verification before programming, validating the JEDEC file and eliminating errors

VHDL Synthesis

• Features IEEE Standard 1076-1993/1164 VHDL synthesis integrated with SynarioÆs Project Navigator environment, enabling topdown design for complex PLDs and FPGAs
• Robust synthesis subset provides complete access to SynarioÆs device-specific logic synthesis and intelligent device fitting technology
• Intelligent parser recognizes design-related constructs; unsynthesizable VHDL constructs (such as timing and waveform specifications) are either ignored or flagged by the compiler
• Wide range of synthesis capabilities provides complete, easy access to SynarioÆs intelligent device-mapping technology - automatically mapping VHDL into a targeted device

Synario FPGA Express - Advanced Verilog and VHDL Synthesis

• Features SynopsysÆ FPGA Express integrated with SynarioÆs Project Navigator environment, to achieve optimum quality of results
• VHDL and Verilog Synthesis expertise is built in for fast and efficient design of complex PLDs and FPGAs
• Implementation Manager allows quick creation and analysis of design alternatives
• Spreadsheet entry of design requirements enables users to easily guide FPGA Express to obtain desired performance and area results
• Architecture specific optimization technology delivers device independence while ensuring efficient use of silicon resources for both area and performance
• Plug and play with Programmable IC Entry, SynarioÆs best-in-class simulators, and vendor-specific place-and-route tools guarantees seamless integration of FPGA Express into SynarioÆs Programmable IC Design Solution

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